This invention relates to a correlation circuit, and more particularly, to a variable clock rate correlation circuit for use in a portable CDMA receiver.
Correlation circuits are commonly used in portable telecommunications receivers for identifying which transmission among many signals is intended for the particular receiver. The correlation circuit generates a locally generated signal and compares that local signal to the received signal. When the received signal and the locally generated signal have a high degree of correlation, the transmission is deemed to be intended for the receiver. When the resulting correlation is low, the transmission is deemed not intended for the receiver and discarded. The received and locally generated signals may be either analog signals, such as those used in FM telecommunications systems, or sequences of binary data in digital systems such as Code Division Multiple Access (CDMA) systems.
Correlation circuits are used throughout the receiver, including in the carrier lock loop and delay lock loop circuitry of the receiver. A carrier lock loop (CLL) is used to remove the carrier offset frequency and phase of the received signal. A delay lock loop (DLL) is used to maintain signal lock, i.e., maintain the alignment between the received and locally generated signals once the received signal has been acquired.
FIG. 1A illustrates a system block diagram of a carrier lock loop (CLL) for a digital CDMA receiver. The CLL includes a complex multiplier 102, a correlation circuit 103, an arc-Tangent look up table (ATAN LUT) 104, a loop filter 105, and a numerically controlled oscillator (NCO) 106. Using a CDMA receiver front end (not shown), a CDMA signal is received and downconverted to baseband I and Q data sequences 101a and 101b. 
The I and Q data sequences 101a and 101b are supplied to the complex multiplier 102 with complex multipliers sin("PHgr") 106a and cos("PHgr") 106b. The complex multipliers 106a and 106b operate to remove the carrier frequency and phase offset from the carrier signal. The I and Q data sequences 102a and 102b are correlated with locally generated sequences (not shown), producing complex phase error components cos("PHgr")xe2x80x2 101a and sin ("PHgr")xe2x80x2 103b. The complex phase error components 103a and 103b are supplied to an Arc-tangent look-up table 104, which produces a phase error signal 105a. The phase error signal 104a is a measure of how closely aligned the received I and Q data carrier offset phase is to the locally generated phase ("PHgr"). The phase error will be minimum when the received carrier phase and "PHgr" are aligned. A loop filter 105 removes any spurious out-of-band signal components from the phase error signal 103a. The phase error signal is supplied to a numerically controlled oscillator (NCO) 106, which in response produces an improved set of complex multipliers 106a and 106b. 
Once the received sequence is matched to the local PN sequence, the alignment between the two sequences must be closely maintained. FIG. 1B illustrates a block diagram of a delay lock loop for dynamically maintaining alignment between the received and local PN sequences once the two sequences are within a predefined range. The delay lock loop 100 includes correlators 110a-c, filters 120a-c, an adder 122, a loop filter 132, a voltage controlled oscillator (VCO) 134, and a local pseudo-normal (P-N) code generator 136. A received chip sequence 102 is concurrently supplied to correlators 110a-c. The PN generator 136 generates a three local PN sequences 104a-c. The first local PN sequence 104a is punctual with the received PN sequence 102. The correlator 110a produces the response shown in FIG. 1C.
When the alignment between the received PN sequence and the Local PN sequence are varied from xe2x88x92T to T, the second local PN sequence 104b is late with respect to the received PN sequence 102, thereby generating the output response 125 shown in FIG. 1D. The third local PN sequence 104c is early with respect to the received PN sequence 102 generating an output response 125c which is shown in FIG. 1E. The early and late versions of the received and locally generated sequences are typically used in the correlation circuits, as shown below.
An adder 122 is used to sum a negated version of the late response with the early response to generate an error signal 130, shown in FIG. 1F. As shown in FIG. 1F, the error signal 130 has a linear voltage level versus time response over the correlation period xc2x1T/2. Once the locally generated and received sequences are within this range, the DLL dynamically realigns them until the error signal 130 reaches zero, indicating perfect alignment between the two.
A loop filter 132 removes spurious noise from the error signal 130 which may occur during the correlation process. The filtered error signal is supplied to the VCO 134, which generates a tone corresponding to the error signal 130. The local PN generator 136 receives the VCO tone, and in response, adjusts the timing of its internally generated local PN sequences 104a-c, either advancing or delaying the local PN sequences 104a-c according to error signal response of FIG. 1F. The adjusted local PN sequences 104a-c are then output to the correlators 110a-c to obtain a higher degree of correlation with the received PN sequence.
Correlation circuits consume power primarily as a function of its operating speed or correlation rate. A correlation circuit operating at a high clock rate consumes more power than the correlation circuit operating at a lower clock rate.
In conventional receiver circuitry such as the aforementioned CLL and DLL, the correlation rate is maintained at a constant clock rate, typically many times higher than the chip rate of the received signal or sequence. The cumulative effect of a large number of correlation circuits operating at a relatively high clock rate results in a significant consumption of power. In light of the limited power supply available to portable cellular telephones, the present method of operating the correlation circuits become very disadvantageous.
What is needed is a new correlation circuit and method of operation which allows a reduction in the clock rate and accordingly, a decrease in power consumption.
The present invention provides for a variable clock rate correlation circuit which conserves power by operating at two different clock rates. During initial signal acquisition, the variable clock rate correlation circuit operates at a high clock rate, 2 or more times the chip rate to correlate the received and locally generated sequences for a possible match. Once the received and local generated sequences exhibit a high degree of correlation, the relative positioning of the received and locally generated sequences is known to a large degree. The variable clock rate correlation circuit then switches to a lower clock rate, less than twice the chip rate, reducing the amount of power it consumes, while maintaining a high degree of time alignment accuracy.
In one embodiment, the correlation circuit includes a variable clock source, a local PN source, and a correlator. The local PN source further includes a local generator and a resampler. The variable clock source provides a normal clock rate and a lower clock rate. The local generator supplies the local PN sequence at the normal clock rate. The resampler receives the local PN sequence sampled at the normal clock rate and outputs the local PN sequence sampled at the lower clock rate. The correlator receives the lower sampled local PN sequence, the received PN sequence, and the lower clock rate signal, correlating the received and local PN sequences at the lower clock rate to produce a correlated result.